Integrated circuits (ICs) comprise a large number of circuit elements, such as transistors, interconnected by a large number of wires. Some elements (“drivers”) drive other elements (“driven elements”). Fanout of a given driver is the number of driven elements coupled to the output of the driver.
The “ramptime” of a driven element is the time required to drive a driven element to operation. Ramptime depends on the amount of capacitance and resistance “seen” by the driver, which in turn depends on the number of driven elements connected to the output of the driver and the length of the wires that interconnect the driver with its driven elements. If a driver's load exceeds a design threshold, the ramptime for the driven elements will also exceed a threshold.
It is common to selectively insert buffers, in the form of additional drivers, between the driver and the driven elements to reduce the number of driven elements for a given driver, thereby minimizing capacitance and resistance “seen” by that driver and minimizing timing violations. However, each added buffer increases power consumption of the integrated circuit. Consequently, it is desirable to minimize the number of buffers. Moreover, because each buffer introduces a delay in signal propagation, it is also desirable to minimize the number of levels of buffers and to minimize the overall interconnect length.
In the hierarchical design flow of digital systems, interconnect information is available only at lower levels of the design process. For example, coupling capacitance information is available only after detailed routing is completed, and not at the higher logic synthesis, placement and global routing stages. While lower levels of the design process provide more detailed interconnect information, the circuit design is usually so advanced at the lower levels that only minimal changes to the circuit structure can be performed to improve performance.
If a clock network is implemented after detailed routing, it is difficult to implement clock logic changes without changing the placement and the routing of data logics. It is also difficult to place the buffers and route the clock nets simultaneously in order to take into account the coupling and other detailed information of the chip fabrication and materials (“silicon information”).
To achieve the overall optimal results from the design specification to implementation, it is crucial to estimate the interconnect information at higher levels of the design process, such as during the placement stage and before routing, where there exists more freedom to restructure the design. Clock logics are very important and also sensitive to the timing closure of a design. A mis-estimation of clock delays may cause thousands or more violated timing paths, and attempts to correct a poorly routed clock net may inadvertently cause other timing violations. Therefore, good delay estimations for the clock logics are important at early stages of the design process. It is also important to implement the clock logics so that they are robust with respect to the interconnect implementations in fabrication of the chip.
A calculated clock delay will unavoidably have estimation errors. To compensate this estimation error, a “clock uncertainty” factor is employed in the estimation of clock delays. To make sure that the circuit under design will operate satisfactorily when implemented into a chip, the value of clock uncertainty is usually set conservatively. However, a conservative clock uncertainty value leads to other problems, such as adding unnecessary buffers to fix timing violations.